The present invention relates in general, to Phase-Locked Loop (PLL) devices and, more particularly, to the stability of a Voltage-Controlled Oscillator (VCO) in a PLL.
Communications systems and computer systems have components that operate at different frequencies. Typically, these systems use Phase-Locked Loops (PLLs) for synchronization of their components. PLLs are widely used for clock generation in data communication systems, local area networks, data storage applications, disc drives, and microprocessors. A PLL generally includes a phase detector, a loop filter, a Voltage-Controlled Oscillator (VCO), and a loop divider. The phase detector receives a reference clock signal and a loop clock signal and provides a phase detect output signal that indicates the phase difference between the loop clock signal and the reference clock signal. The phase detector provides the phase detect output signal to an input of the loop filter, which in turn provides a filtered signal to the VCO. The filtered signal provides a voltage that adjusts the frequency and phase of the clock output signal generated by the VCO. The clock output signal is divided by the loop divider to provide the loop clock signal. When the loop clock signal is synchronized to the reference clock signal, these two signals have the desired phase-frequency relationship and the PLL is locked.
In some systems, it is desirable to switch the reference clock signal between one of two clock signals, i.e., a primary clock signal and a backup clock signal. A multiplexer is used to switch between the two clock signals. During normal operation, the primary clock signal serves as the reference clock signal. In the event of a failure of the primary clock signal, the select input of the multiplexer is toggled such that the backup clock signal becomes the reference clock signal. If the primary clock signal and backup clock signal are out of phase, then the PLL changes the frequency of its output signal to regain phase lock to the new reference clock signal, i.e., the backup clock signal.
The phase detector uses latches to detect the phase-frequency relationship between the reference clock signal and the loop clock signal. The latches switch states at the transition edges of the reference clock and the loop clock signals. The width of the pulses at the outputs of the latches indicate a phase relationship between the reference clock and the loop clock signal. When the primary clock signal fails, the phase detector does not receive a signal transition for the primary clock, causing the phase detector to generate an abnormally wide pulse. By the time the detection circuitry detects that the primary clock has failed and the multiplexer switches to the backup clock signal, the PLL changes frequency in response to the abnormally wide pulse. The PLL drifts from the desired phase-frequency relationship of the locked condition.
Accordingly, it would be advantageous to have a PLL device and a method for reducing the drift in frequency and phase when the reference clock signal fails. It would be of further advantage to have a PLL that minimizes the amount of time it takes to regain phase lock when the PLL device receives a backup reference clock signal.